1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and especially to a semiconductor integrated circuit device having a field-effect transistor including a gate electrode formed as a ring shape, a source diffusion layer outside of this gate electrode and a substrate potential diffusion layer or a well potential diffusion layer formed outside the source diffusion layer.
2. Description of Related Art
In recent years, in semiconductor integrated circuit devices, miniaturization of manufacturing process and reduction of operating power supply voltage are developing. In such a semiconductor integrated circuit device, a soft error called Single Event Upset (SEU) occurs when radiation or the like hits a memory cell, a flip-flop circuit (hereinafter referred to as a F/F circuit) and a field-effect transistor for forming an information storage circuit such as a latch circuit and a logical circuit which is to be a transmitting channel of a signal (the field-effect transistor merely referred to as a transistor as appropriate). When this soft error occurs, logic information held in the transistor is reversed and there is a problem that a defect is generated in subsequent signal processing.
The countermeasure technique for this soft error is disclosed in Japanese Unexamined Patent Application Publication No. 2003-273709 (Arima, et al.). Arima, et al. discloses that a transistor is added to a circuit and suppressed generation of the soft error by devising the circuit configuration. Moreover, the related art discloses to suppress from generating the soft error by adding capacity to the information storage node of the circuit.
In order to reduce Soft Error Rate (SER), it is necessary to recognize the cause of the soft error. Thus, the cause of generating the soft error is explained hereinafter. Soft errors are generated by a carrier generated in a substrate region (including a well region of a transistor hereinafter) due to a burst of radiation or a charged particle into a diffusion layer of an information storage node. For example, when the information storage node diffusion layer formed with an N-type semiconductor holds high level (hereafter referred to as H level), if a charge flows into this node, the information storage node diffusion layer will become low level (hereafter referred to as L level) from H level. On the other hand, when the information storage node diffusion layer formed with a P-type semiconductor holds L level, if a charge flows into this node, the information storage node diffusion layer will become H level from L level. How the carriers generated in the substrate region are collected to the information storage node diffusion layer is disclosed in Eiji Takeda, et al., “A Cross Section of α-Particle-Induced Soft-Error Phenomena in VLSI's”, IEEE TRANSACTION ON ELECTRON DEVICES, Vol. 36, No. 11, pp. 2567-2575, 1989.
Moreover, as another phenomenon of influencing SER, there is information reversal phenomenon due to parasitic bipolar transistor operation. If electrons and electron holes are generated in large quantities near a source diffusion layer of a transistor, a parasitic bipolar transistor which uses a source as an emitter, substrate as a base and a drain as a collector is formed. Operation of this parasitic bipolar transistor reduces (or increases) the potential of the drain and reverses the information stored in the node. This is disclosed in Kenichi Osada, et al., “SRAM Immunity to Cosmic-Ray-Induced Multierrors Based on Analysis of an Induced Parasitic Bipolar Effect”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 39, No. 5, pp. 827-833, 2004.
The technique to suppress this information reversal by a parasitic bipolar transistor is disclosed in T. Calin, et al., “Topology-Related Upset Mechanisms in Design Hardened Storage Cells”, RADECS98, Fourth European Conference on Radiation and Its Effect on Components and System, pp. 484-488, 1998 (Calin, et al.). In Calin, et al., BBD (Bulk Bias Diffusion, hereinafter referred to as a subcontact) is provided between source diffusion layers and between drain diffusion layers of adjacent transistors. Then in the related art, a potential of a substrate region is stabilized to suppress the parasitic bipolar transistor from operating.
However, miniaturized transistors in recent years have small size of devices and distance between adjacent devices is also close. Therefore, distance of an area having a potential to reverse approaches and a distance of the portion operating as a base region of a parasitic bipolar transistor becomes substantially shorter. This will make the parasitic bipolar transistor easier to operate, thus there is a problem that operation of a parasitic bipolar transistor cannot be sufficiently suppressed only by subcontact. This is explained below.
FIG. 18 is an example of the layout of a transistor according to a related art when viewed from the top. As shown in FIG. 18, the transistor of a related art has a subcontact (BBD in FIG. 18) between the source diffusion layers (S1 and S2) of adjacent transistors. Moreover, a cross-sectional diagram of the transistor taken along the line X19-X19′ of FIG. 18 is shown in FIG. 19. As shown in FIG. 19, the subcontact is formed between the source diffusion layers (S1 and S2) of adjacent transistors. However, as for the transistor in recent years, the distance between source diffusion layer and drain diffusion layer has become extremely short by miniaturization. Therefore, the distance of the base region of a parasitic bipolar transistor (the distance between a drain diffusion layer D1 and a drain diffusion layer D2 in FIG. 19) is short and it is in the state where the parasitic bipolar transistor operates easily.
For example, when the drain diffusion layer D1 of a transistor Tr1 is L level and the drain diffusion layer D2 of a transistor Tr2 is H level, as the distance between the drain diffusion layer D1 and the drain diffusion layer D2 is short, a parasitic bipolar transistor using the drain diffusion layer D1 as an emitter, the drain diffusion layer D2 as a collector and a substrate region as a base operates. Operation of this parasitic bipolar transistor inverts H level of the drain diffusion layer D2 to L level.
In addition, as another example, the layout of a semiconductor device having a different layout from FIG. 18 when viewed from the top is shown in FIG. 20. In the semiconductor device shown in FIG. 20, transistors Tr1 and Tr2 are disposed to be adjacent. Then, drain diffusion layers of the two transistors are adjacent with a subcontact formed in between. Moreover, a transistor Tr3 is formed in the distant area from a source diffusion layer S2 of the transistor Tr2 so that the drain diffusion layer D3 may be on the side of the source diffusion layer S2.
Furthermore, a cross-sectional diagram of the transistor taken along the line X21-X21′ of FIG. 20 is shown in FIG. 21. As shown in FIG. 21, a subcontact is formed between the drain diffusion layers (D1 and D2) of adjacent transistors. However, a parasitic bipolar transistor is formed between transistors Tr2 and Tr3 that are disposed to be adjacent without intervening the subcontact. In the example shown in FIG. 21, when the drain diffusion layer D3 of the transistor Tr3 is H level, a parasitic bipolar transistor using the source diffusion layer S2 as an emitter, a substrate region as a base and the drain diffusion layer D3 as a collector is formed. The operation of the parasitic bipolar transistor causes an information reversal, reversing the drain diffusion layer D3 of the transistor Tr3 from H level to L level.
On the other hand, when the drain diffusion layer D3 of the transistor Tr3 is L level and the drain diffusion layer D2 of the transistor Tr2 is H level, a parasitic bipolar transistor using the drain diffusion layer D3 as an emitter, a substrate region as a base and the drain diffusion layer D2 as a collector is formed. The operation of the parasitic bipolar transistor causes an information reversal, reversing the drain diffusion layer of the transistor Tr2 from H level to L level.
As a defect produced by operation of a parasitic bipolar transistor, there is latch-up. The latch-up is a defect in which a parasitic bipolar transistor operates and a current flows in a path different from the normal operation. The technique to deal with this latch-up is disclosed in Japanese Unexamined Patent Application Publication Nos. 2005-159131 and 62-262462.
In Japanese Unexamined Patent Application Publication No. 2005-159131, in order to stabilize a well potential of a transistor forming a SRAM (Static Random Access Memory), butted contact is used. This further stabilizes the well potential to suppress operation of a parasitic bipolar transistor Moreover, in Japanese Unexamined Patent Application Publication No. 62-262462, operation of a parasitic bipolar transistor is suppressed by a guard band diffusion layer surrounding a transistor. At this time, this guard band diffusion layer may be a butted contact structure. Moreover, in Japanese Unexamined Patent Application Publication No. 62-262462, the total dose effect generated by the quantity of received radiation is prevented. This total dose effect is a phenomenon in which device characteristics of a transistor are degraded by the quantity of received radiation (leakage characteristics degradation).
Moreover, the technique to prevent the degradation of the leakage characteristics by this total dose effect is disclosed in Donald C. Mayer, et al. and “Reliability Enhancement in High-Performance MOSFETs by Annular Transistor Design”, IEEE TRANSACTION ON NUCLEAR SCIENCE, Vol. 51, No. 6, pp 3615-3620, 2004. A gate electrode formed as a ring shape is used in this technique. Other examples of using such transistor with a ring gate are disclosed in K. Yuzuriha, et al., “A Large Cell-Ratio and Low Node Leak 16M-bit SRAM Cell Using Ring-Gate Transistors”, 1991 International Electron Devices Meeting, pp. 485-488, 1991, Japanese Unexamined Patent Application Publication No. 9-330986 and U.S. Pat. No. 6,097,066. The technique disclosed by K. Yuzuriha, et al. is to increase the effective area of a transistor by making a gate electrode a ring to reduce the cell size of SRAM. This example also discloses to reduce SER as the area of a memory node region is reduced.
In an example disclosed in Japanese Unexamined Patent Application Publication No. 9-330986, by forming a gate electrode as a rectangle or a ring and forming a diffusion layer corresponding to the gate electrode, when an α particle travels inside a semiconductor substrate, distance in which the particle travels a diffusion layer portion of a transistor is made shorter. In Japanese Unexamined Patent Application Publication No. 9-330986, by such layout, the amount of electric charge collection to an information storage node is reduced to improve SER.
The example disclosed in U.S. Pat. No. 6,097,066 is about a transistor having a gate electrode of ring shape used for a device for electro-static discharge protection (hereinafter referred to as a ESD protection device). In this transistor, a source diffusion layer is formed outside the gate electrodes formed in a ring shape and a substrate potential diffusion layer is formed further outside. Moreover, in this transistor, one transistor is formed by dividing into 4 transistor regions. Generally an ESD protection device connects each terminal of the transistor divided in this way to the same line. Moreover, in the normal operation of a semiconductor device, each terminal is connected so that the transistor may not operate.
We have now discovered that in related arts, there is a problem that it has not been sufficient to suppress the electric charge collection to an information storage node and a drain diffusion layer of a logical circuit and to prevent the information reversal by a parasitic bipolar transistor and thus SER has not been reduced sufficiently.